The invention relates to a NAND type flash memory device and a method for fabricating the same. More specifically, the invention relates to a NAND type flash memory device with improved operation speed and a method for fabricating the same.
NAND type flash memory devices are electrically programmable and erasable non-volatile memory devices. NAND type flash memory devices are widely utilized in applications including portable electronics (e.g., MP3 players, digital cameras, camcorders, notebook computers, PDAs, and cellular phones), computer BIOSs, printers, and USB drives.
FIG. 1 shows an equivalent circuit of a NAND type flash memory device.
A memory cell array includes a plurality of cell strings connected to associated bit lines, BL1, BL2, . . . . Each unit cell string includes a source select transistor (SST), memory cells M1-M32, and a drain select transistor (DST). Each drain select transistor (DST) is connected to the one of bit lines, BLe and BLo. Each source select transistor (SST) is connected to a common source Ine (CSL). The memory cells M1-M32 are serially coupled between the source select transistor (SST) and the drain select transistor (DST). The number of memory cells included in one cell string is varied depending on the storage capacity of memory device used. The gate of the source select transistor (SST) at each cell string is commonly connected to a source select line (SSL). The source select line (SSL) transmits a string select signal supplied from a row decoder. A drain select line (DSL) transmits a drain select signal supplied from the row decoder. The drain select line (DSL) is connected to the gate of the drain select transistor (DST). The control gates of the memory cells M1-M32 are coupled to word lines WL1-WL32, respectively.
A memory cell includes a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate. In the source select transistor (SST) and the drain select transistor (DST), a first polysilicon layer for the floating gate is in contact with a second polysilicon layer for the control gate via a contact hole passing through the intergate dielectric layer. When the contact resistance between the first polysilicon layer for floating gate and the second polysilicon layer for the control gate abnormally increases, signal transmission is delayed and chip failure occurs, thus causing a significant deterioration in fabrication efficiency.
The increased contact resistance is due to a polymer or a parasitic oxide layer formed while etching of the dielectric layer and remaining due to incomplete removal by an etchant, prior to deposition of the second polysilicon layer. In addition, because the contact between the first polysilicon layer and the second polysilicon layer inherently has a high resistance, a delay in signal transmission of the SSL and DSL and an occurrence of chip failure result.